An image sensor, which can be either a CCD (charge coupled device) or a CMOS (complementary metal oxide silicon) image sensor, is an important component of a digital camera. Recently, the CMOS image sensor has been widely used due to its high pixel sensitivity, short exposure time and decreased pixel size. As one of the most important performance indicators of the CMOS image sensor, the pixel sensitivity is determined by the product of the pixel fill factor (the ratio of the photosensitive area and the total pixel area) and the quantum efficiency (the number of the electrons converted from the incident light).
The conventional CMOS image sensor utilizes Front Side Illumination (FSI) technology. In a FSI image sensor, photodiodes, metal layers and micro-lens are manufactured in order from the front side of the substrate and light pipe channels are created through the metal layers allowing for light travelling from the micro-lens to the photodiodes. The FSI technology has the advantages of simple process, high compatibility with the CMOS process and low cost. Furthermore, since the filling material in the light pipe channel can be changed to achieve different refractive index, the transmissivity of the incident light can be promoted and the crosstalk between the adjacent pixels can be reduced. However, with the reduction of the pixel size, it is increasingly difficult to improve the fill factor of the FSI image sensor. One solution is to use back side illumination (BSI) technology. During the fabrication of a BSI image sensor, the photodiodes and the metal layers are firstly formed in the front side of the substrate, then the substrate is thinned from its backside (usually to the thickness of less than 20 um), then Through-Silicon-Via (TSV) technology is performed to lead out the signal from the photodiodes. Since the interconnection circuits are formed at the backside of the substrate and the entire front surface is reserved for the photodiodes, the BSI image sensor is advantageous to provide higher fill factor. Due to the cost consideration and the substrate thinning process restriction, the BSI technology is always applied to the image sensors with small pixel size, such as the camera of the smart phones
Generally, the bigger pixel area of a pixel unit will lead to higher sensitivity and larger dynamic range. In the current Single Lens Reflex camera (SLR camera), micro Single Lens Reflex camera, High-definition monitor and other CMOS image sensor application fields, FSI image sensors with bigger pixel areas are usually utilized. On the other hand, pixels with smaller size are also desired to decrease the size of the image sensor. As a result, the requirements for higher sensitivity and lower size make contradictory.
Accordingly, it is necessary to provide a new image sensor to solve the problem. In the prior art, an image sensor capable of performing pixel binning and pixel splitting is proposed. As shown in FIG. 1, the image sensor adopts column analog-to-digital conversion (ADC) system architecture by arranging a plurality of column ADC modules 4 on one side or opposite sides of the pixel array module 1, wherein each column ADC module 4 corresponds to one or two columns of the pixel array. A decode module 2 is configured to select one row of the pixel array, control the PGA (programmable gain amplifier) module 3 to successively amplify the split pixel data or the binned pixel data of each row, and control the column ADC modules to convert the data into digital data and output the digital data in sequence by the shift registers thereof. However, since the layout of the column ADC modules is much bigger, the image sensor capable of performing pixel binning and pixel splitting based on the column ADC modules usually requires large pixel size. For those image sensors having smaller pixel size (the pixel size is no more than 2.5 μm), since the space reserved for the layout of the column ADC modules is only 2.5 μm or 5 μm, the column ADC system architecture is unsatisfied.